The present invention relates to a low-power CMOS device and logic gates/circuits therewith and, more particularly, to electrical circuits having enhanced noise tolerance.
Complementary metal-oxide-semiconductor (CMOS) devices and circuitry are used extensively to implement digital logic circuits. CMOS circuitry exhibits two exemplary characteristics: low-power consumption and high noise tolerance.
Because of these characteristics and because such circuitry is relatively inexpensive to fabricate and has relatively high reliability, CMOS devices, rather than bipolar and N-type MOS transistors, are predominately used to make integrated circuits.
The elemental CMOS circuit is a conventional CMOS inverter 100, illustrated in FIG. 1A. The CMOS inverter 100 includes a N-type MOS field effect transistor (N-MOSFET) 120 and a P-type MOS field effect transistor (P-MOSFET) 140 coupled in series. The gate electrodes 160 and 180, respectively, of the N-MOSFET 120 and the P-MOSFET 140 are coupled together to form the input 190 of the conventional CMOS inverter 100. Drain/source nodes of the N-MOSFET 120 and P-MOSFET 140 are coupled together to form the output 170 of the conventional CMOS inverter 100. The other source/drain nodes and the body connections of the P-MOSFET 140 and the N-MOSFET 120 device are respectively coupled to a supply voltage Vdd 130 and to ground (GND) 150. As used herein, the terms source/drain (and drain/source) are used to refer to both drain and source regions of MOSFET transistors. This nomenclature reflects the interchangeability of the drain and source regions in a MOSFET device, where a particular designation of source or drain depends on the voltages applied to each of these regions.
Operation of the conventional CMOS inverter 100 is well known to persons skilled in the art of circuit design. The corresponding voltage transfer characteristic (VTC) 101 (i.e., Vout versus Vin plot) for the conventional CMOS inverter 100 is illustrated in idealized form in FIG. 1B. The VTC 101 includes four operating regimes, I, II, III, IV, that occur when switching from one logic state to the other. In regime I, the P-MOSFET is ON and the N-MOSFET is OFF, in region II, the P-MOSFET is in its linear region while the N-MOSFET is in saturation, in region III, the P-MOSFET is in saturation while the N-MOSFET is in its linear region, and, lastly, in region IV, the P-MOSFET is OFF and the N-MOSFET is ON. At the transition between regimes II and III, both the N-MOSFET and the P-MOSFET are simultaneously conducting; as discussed below, it is at this transition that the circuit is momentarily short-circuited between Vdd and circuit ground 150. The VTC 101 of the conventional CMOS inverter 100 illustrates that the voltage logic level at the output 170 is the logical inverse of the voltage logic level at the input 190.
At least three sources of power dissipation exist in a CMOS circuit, such as the conventional CMOS inverter 100 of FIG. 1A:
(1) switching power dissipation;
(2) short-circuit power dissipation; and
(3) static power dissipation resulting from reverse-biased PN junction leakage currents.
The switching power is the power dissipated each full cycle due to the successive charging and discharging of the capacitive load tied to the output node of a CMOS circuit (e.g., output 170 of the conventional CMOS inverter 100). Switching power is generally the largest component of total CMOS circuit power dissipation. CMOS circuit switching power consumption may be significantly reduced by diminishing the load capacitance coupled to the output of the CMOS circuit. Such load capacitance is typically the input capacitance of a successively coupled CMOS circuit. CMOS circuit input capacitance (e.g., load capacitance) is principally reduced by reducing MOSFET gate lengths in the CMOS circuits.
Short-circuit power consumption is the momentary direct-path DC power that is dissipated by the CMOS circuit each time its logic input conditions cause its output to change from one logic state to the other logic state. Short-circuit power consumption is due to the short-circuit path that arises at the transition between regimes II and III in FIG. 1B during output state changes when the serially coupled N-MOSFET 120 and P-MOSFET 140 are simultaneously conductive (e.g., turned ON), so that current flows from a power supply Vdd to ground 150. During this conduction period (i.e., when both MOSFETs 120, 140 are simultaneously substantially turned ON), short-circuit power is dissipated in the MOSFETs output conductances and parasitic resistances. While the conduction period for short-circuit current is very short for each logic state transition, at higher switching speeds, the conduction period can become a successively higher and more significant fraction of the clock cycle resulting in significant short-circuit power dissipation.
Finally, static leakage power consumption is due to the small leakage currents that arise from reverse-biased PN junctions (and sub-threshold effects). Static leakage power consumption is generally the smallest component of total CMOS circuit power dissipation.
In addition to their relatively low power consumption, CMOS circuits, operating at conventional supply voltages (e.g., five volts), have relatively high noise tolerance, and thus are more accepting of variations in input signal levels.
The high noise tolerance of CMOS circuits better assures the accuracy of CMOS circuit signal processing, even in relatively noisy environments.
Having a relatively high noise tolerance permits a CMOS circuit to interpret input signals within a relatively large voltage range near either logic state voltage (e.g., outside a relatively small range approximately centered at one-half the power supply voltage) as either a logic xe2x80x980xe2x80x99 or as a logic xe2x80x981xe2x80x99. This ability allows CMOS circuitry to better tolerate noise, for example, generated within or outside of the CMOS circuitry as will be later described.
Such enhanced noise tolerance for CMOS circuitry may be quantified by a measures known as noise margins. FIG. 1B illustrates four output and input voltage levels, of the conventional CMOS inverter 100, used to quantify noise tolerance.
1. Voh=Minimum logic xe2x80x981xe2x80x99 output voltage (20)
2. Vol=Maximum logic xe2x80x980xe2x80x99 output-voltage (40)
3. Vih=Minimum input voltage recognized as logic xe2x80x981xe2x80x99 (80)
4. Vil=Maximum input voltage recognized as logic xe2x80x980xe2x80x99 (60)
Typically, Voh 20 equals the supply voltage (Vdd) 130 and Vol 40 equals zero volts, or ground (GND) 150.
Two noise margins (respectively, for the high, or logic xe2x80x981xe2x80x99, and low, or logic xe2x80x980xe2x80x99, states) may be defined as follows:
1. Noise Margin High: NMH=Vohxe2x88x92Vih 
2. Noise Margin Low: NML=Vilxe2x88x92Vol 
High noise margins, or tolerance to variations in the signal level, are especially valuable in environments having circuit noise that can significantly corrupt signals. The circuit noise may be undesirable signals coupled to the CMOS circuit. Such circuit noise may be coupled from neighboring transmission lines (e.g., in a highly integrated circuit) or coupled from other sources by capacitive or inductive coupling. Such noise may cause the voltage level at a node in a CMOS circuit to significantly vary, potentially affecting the logic states at that and other circuit nodes. The high noise tolerance of CMOS circuits generally ensures that both noisy and noiseless input signals presented to a CMOS circuit are interpreted properly.
Because transistor dimensions are continuing to decrease, the density (e.g., device density) of CMOS integrated circuits continues to increase. As a result, CMOS circuit noise margins are undesirably declining as device density increases.
Increased density increases the power dissipation per unit area of CMOS circuits; increased power dissipation may diminish CMOS circuit reliability.
Further, the power consumption of highly integrated CMOS circuits may increase beyond the capacity of available power supplies. Thus, to diminish power dissipation, CMOS circuit power supply voltage levels have been reduced, for example, from 5 volts to 3.3 volts to 2.5 volts and to 1.8 volts. The reduction of power supply voltages has detrimentally diminished CMOS circuit noise margins because of the corresponding reduction of Voh 20, Vol 40, Vih 80, and Vil 60. Further, the use of lower power supply voltages has given rise to an even greater need for higher CMOS circuit noise margins. CMOS circuits operating with reduced supply voltages may incorporate voltage level conversion circuitry to provide, for example, higher voltage levels within the CMOS circuits. Such conversion circuitry, however, can significantly increase noise levels within the CMOS circuits. Also, as both circuit density and operating speeds rise, capacitively and inductively coupled noise is increased in the CMOS circuits.
A Schmidt trigger 151, illustrated in FIG. 1C, is a switching inverter that has higher noise margins than a conventional CMOS inverter 100. One common application of Schmitt triggers 151 is to provide a clean square-wave voltage output for any applied input voltage waveform when any portion of the input waveform exceeds the triggering threshold of the Schmidt trigger. The Schmidt trigger 151 includes six transistors 152, 153, 154, 155, 156, and 157. Hence, the Schmidt trigger 151 is relatively large in comparison to the conventional CMOS inverter 100, and thus more expensive to fabricate. Further, the Schmidt trigger 151 dissipates more power than the conventional CMOS inverter 100.
Therefore, there is a need for increased noise margins in state-of-the-art CMOS circuits operating at relatively low power supply voltages. Further, because digital logic switching speeds are increasing, there is a need to diminish short-circuit power dissipation in state-of-the-art CMOS circuits. Additionally, there is a need to minimize the size of such circuits.
The above-mentioned problems with CMOS circuitry and other problems are addressed by a device according to the resent invention, which includes a field effect transistor and an interconnect having gate and wiring regions where the interconnect forms a gate of the field effect transistor in the gate region thereof and includes a diode junction formed therein in the wiring region. The diode junction imparts a diode characteristic between portions of the wiring region and the transistor.
Typically, the interconnect includes polycrystalline semiconductor material such as polysilicon. The interconnect may also include a silicide layer disposed in a conducting relationship with the polycrystalline semiconductor material. However, the silicide layer is absent in a diode region surrounding the diode junction of the interconnect. The diode region acts to delay transistor turn-ON relative to transistor turn-OFF, which effect may be exploited to reduce power dissipation and increase noise immunity of circuits employing the devices according to the present invention.
In accordance with another aspect of the present invention, a logic circuit having enhanced noise immunity includes at least two transistors and an interconnect forming a gate of the at least two transistors in at least two gate regions. The interconnect also forms a wiring region outside of the gate regions. The interconnect further includes at least two diode junctions formed therein in the wiring region, the diode junctions imparting diode characteristics between a portion of the wiring region and the gate regions.
In accordance with another aspect of the present invention, a circuit having enhanced noise immunity includes a pair of transistors, each including a gate. A pair of diodes serially couples a signal to respective ones of the gates. In so doing, the diodes affect the transition of the transistors between their ON and OFF states in response to transitions of the drive signal, where the transition from ON to OFF is faster than the transition from OFF to ON.
In accordance with another aspect of the present invention, an apparatus includes-an electronic system and a memory and/or processor coupled to the electronic system. The memory or processor coupled to the electronic system includes a pair of transistors, each having a gate and a pair of diodes. Each of the diodes serially couples a signal to respective ones of the gates. In so doing, the diodes affect the transition the transistors between their ON and OFF states in response to transitions of the signal. The diodes affect the transition of the pair of transistors from ON to OFF faster than from OFF to ON.
In accordance with another aspect of the invention, a method of fabricating a transistor in a semiconductor includes first and second steps of forming and an implanting step. In the first forming step, a polycrystalline semiconductor is formed over a gate oxide in a gate region and over a field oxide in a wiring region of the semiconductor. In the implanting step, impurities are implanted into the semiconductor to form a transistor in the gate region and a diode junction in the wiring region of the polycrystalline semiconductor. Then in the second forming step, a conductive coating is formed on the polycrystalline semiconductor except in a region around the diode junction. Typically, the polycrystalline semiconductor is polysilicon and the conductive coating is silicide. However any other suitable materials that provide the desired functionality may be used.
In accordance with another aspect of the invention, a method of operating a device that includes a field effect transistor and an interconnect forming a gate of the field effect transistor is provided. The interconnect has an input terminal and a diode junction between the input terminal and the gate. The method includes applying and propagating steps. In the applying step, a signal is applied to the input terminal and, in the propagating step, the signal is propagated through the diode junction to the gate.
In accordance with another aspect of the invention, a method of imparting enhanced noise immunity to a circuit includes steps of dividing, conveying, and delaying or slowing. In the dividing step, a received signal is divided into first and second signals. Then, in the conveying step, the first and second signals are separately conveyed to respective first and second transistors. In the delaying or slowing step, signal transitions on the signals conveyed to each of the first and second transistors are slowed when the signal transition tends to transition the corresponding transistor ON.
The gate structure and gate connection in accordance with the transistors, logic circuit family, and integrated circuits designed and fabricated in accordance with the invention provide a gate structure and connection that includes an asymmetrical conduction function, preferably with an exposed diode junction that provides hysteresis to improve noise immunity and preferably delays the turn-ON time relative to the turn-OFF time to maintain one transistor of a CMOS pair of transistors in the OFF state during part or all of the switching turn-OFF period of the other and thus reduce short-circuit power consumption and dissipation. A series-connected polycrystalline diode having reduced forward conduction current and increased reverse leakage current in comparison with single crystalline diodes is a preferred component of the gate structure and connection providing the desired asymmetric conduction and transistor switching function. The transistor design and fabrication need not otherwise be altered to accommodate inclusion of the invention.
It is therefore an object of the present invention to provide a CMOS logic circuit family having significantly improved noise immunity and reduced power consumption.
It is another object of the invention to provide a CMOS transistor design which provides significantly improved noise immunity and reduced power consumption in digital logic circuits without significant compromise of switching speed.
It is a further object of the invention to provide circuits having a comparable degree of noise immunity and reduced power consumption to known circuits specifically. designed for such purposes but with fewer CMOS transistors and improved performance.